The present invention relates generally to electronic circuits and, more particularly, to efficient clock domain partitioning and clock delay matching.
There is a perpetual need for increased operating speed in electronics circuits used in electronic equipment. For example, circuit designers are continually developing communication circuits and microprocessors that can send and process data, respectively, at faster and faster rates.
However, tradeoffs typically must be made between the speed at which a circuit operates and the power the circuit consumes. In general, a circuit that operates at a higher speed than a comparable circuit will consume more power than that comparable circuit. In many circumstances, there is a-practical limit on the amount of power a given circuit can or should consume. For example, increased power consumption typically results in a higher overall cost for the system. Moreover, certain types of electronic circuits such as integrated circuits can only dissipate a limited amount of power. High power consumption may also have other adverse effects on the operation of a circuit such as reducing the reliability of the circuit and adversely affecting the timing relationships in the circuit.
It has been observed that in some circuits not all of the circuitry has the same speed requirements. That is, some of the circuitry may operate at slower speeds than other circuitry. In this case, multiple supply voltages may be used to reduce the power dissipation of the integrated circuit. Those circuits that are speed sensitive are driven at a higher operating voltage while the less speed critical circuits are driven at a lower operating voltage. As a result, the less speed critical circuit will consume less power.
Typically, signals will be sent between these high-power and low-power circuits. In the case where these signals are referenced to a common system clock signal, the two circuits will be driven by clock signals derived from the common system clock signal. These derived clock signals, in turn, are generated by circuit components that operate at the respective operating voltage. That is, clock signals for the high-power circuits are generated by circuit components that operate at the high operating voltage. Clock signals for the low-power circuits are generated by circuit components that operate at the low operating voltage.
As in virtually all electronic circuits, the circuit components that generate the clock signals induce a delay in signals that pass through them. Moreover, the delay of a given circuit component depends, in general, on the supply voltage. In addition, supply voltages may deviate from their nominal values by certain tolerances, for example, +/xe2x88x9210%. As a result of these delays, the clocks that drive the circuit components that operate at different supply voltages may be skewed in time relative to one another. Moreover, this skew in time may vary over time as the supply voltages deviate within their operating tolerances.
This misalignment of the clock signals in the different domains may result in clock uncertainty. This, in turn, may reduce the available cycle time of the circuit because the clock uncertainty has to be compensated by asynchronous delays when a signal is exchanged between the two domains within one clock cycle. As a result, it may be impossible to double latch the signals. In sum, this misalignment of the clock signals may corrupt data being processed by the circuit.
The invention is directed to systems and methods for providing clock signals to circuits driven by different operating voltages. According to the invention, the clock signals for the circuits driven by the different operating voltages are delayed, as necessary, to reduce the phase difference between the clock signals.
One embodiment of a system constructed according to the invention incorporates a buffer with an adjustable delay to reduce the delay mismatch between clock signals driven by clock trees associated with each operating voltage. A phase detector circuit compares the clock phases for rising and falling edges of the clock signals for each operating voltage. The phase detector circuit controls bias voltages that, in turn, control the delay of the adjustable-delay buffer.
Another embodiment of a system constructed according to the invention incorporates a selector circuit that selectively routes the clock signals for the different operating voltages through an appropriate number of circuit elements to adjust the delay of those clock signals. In this embodiment, the selector circuit is controlled by a phase detector that compares the edges of the clock signals for the different operating voltages.